Single Event Mirroring and DRAM Sense Amplifier Designs for Improved Single-Event- Upset Performance
نویسندگان
چکیده
This paper proposes and investigates schemes for hardening the conventional CMOS cross-coupled DRAM sense amplifier to single event upset (SEU). These schemes, adapted from existing SRAM hardening techniques, are intended to harden the dynamic random access memory to bitline-mode errors during the sensing period. Simulation results indicate that a 9kΩ L-resistor hardening scheme provides greater than 24-fold improvement in critical charge over a significant part of the sensing period. Also proposed is a novel single event (SE) mirroring concept for SEU hardening of DRAMs. This concept has been implemented for hardening the bitlines to hits on diffusion regions connected to the lines during the highly susceptible highimpedance state of the bitlines. It is shown to result in over 26-fold improvement in the level of critical charge using a 2pF dynamic capacitive coupling.
منابع مشابه
Hardened Flip-Flop Optimized for Subthreshold Operation Heavy Ion Characterization of a Radiation
A novel Single Event Upset (SEU) tolerant flip-flop design is proposed, which is well suited for very-low power electronics that operate in subthreshold (<Vt ≈ 500 mV). The proposed flip-flop along with a traditional (unprotected) flip-flop, a Sense-Amplifier-based Rad-hard Flip-Flop (RSAFF) and a Dual Interlocked storage Cell (DICE) flip-flop were all fabricated in MIT Lincoln Lab’s XLP 0.15 μ...
متن کاملUltra Low-Power Fault-Tolerant SRAM Design in 90nm CMOS Technology
.................................................................................................................................. iii TABLE OF CONTENTS ............................................................................................................... iv LIST OF FIGURES ....................................................................................................................
متن کاملReliable Cache Architectures and Task Scheduling for Multiprocessor Systems
This paper proposes a task scheduling approach for reliable cache architectures (RCAs) of multiprocessor systems. The RCAs dynamically switch their operation modes for reducing the usage of vulnerable SRAMs under real-time constraints. A mixed integer programming model has been built for minimizing vulnerability under real-time constraints. Experimental results have shown that our task scheduli...
متن کاملDesign of a ‘Single Event Effect’ Mitigation Technique for Reconfigurable Architectures
Commercially off the shelf (COTS) available reconfigurable System-on-Chip architectures, are becoming popular for applications where high dependability, performance and low costs are mandatory constraints such as space applications. We present a unique SEE (single Event Effect) mitigation technique based upon Temporal Data Sampling and Weighted Voting for synchronous circuits and configuration ...
متن کاملAn improved SRAM cell design for tolerating radiation-induced single-event effects
This paper presents an improved design of a radiationhardened static random access memory (SRAM) cell. The memory cell is designed to be tolerant to transient single-event upsets by taking advantage of the fact that for the same area, the surface mobility of NMOS transistors is greater than that of PMOS transistors. The results show that the proposed design is able to withstand single-event ups...
متن کامل